In the field of integrated circuits, it is preferable to form circuit elements in the smallest achievable surface area, in order to realize a high degree of circuit complexity into a small integrated circuit chip size, resulting in lower cost per function. For circuits containing capacitors, such as those required in analog-to-digital converters (ADCs) and in non-volatile memories which use capacitive coupling between a control gate and a floating gate, the goal of large scale integration requires the provision of capacitors which are small in cross-sectional area but large in capacitance. Especially in the field of ADCs, the stability of the capacitance value over a range of applied voltage, and over a given temperature range, is additionally important in providing fast and accurate conversion.
Another consideration in the cost of fabricating integrated circuits is the complexity of the fabrication process. The process complexity can be increased in an attempt to save surface area by increasing the number of interconnect levels. For example, the surface area of a given integrated circuit may be reduced by using two, rather than one, levels of polysilicon gates and interconnects, under the overlying metallization layer(s). However, the process complexity is increased by including the additional polysilicon layer due to the added process steps of the deposition of an additional polysilicon layer, deposition of an additional dielectric layer, and patterning and etching the additional polysilicon layer and contacts thereto.
Furthermore, additional high temperature process steps performed after the formation of diffused junctions are detrimental to the ability to scale the transistors in an integrated circuit, as the additional high temperature steps cause the diffused dopants used in junction formation to further diffuse, resulting in deeper junctions and wider lateral diffusion.
Furthermore, it is desirable that the manufacturing process flow for the fabrication of integrated circuits such as ADCs be as compatible as possible with the manufacturing process flows for other integrated circuits such as digital logic circuits. However, large value and low voltage coefficient capacitors such as are necessary in ADCs are generally not required in modern digital logic circuits. The incorporation of a special process flow for the fabrication of such capacitors at an early stage in the process would tend to reduce the compatibility of the process for fabricating the ADC with that for fabricating the digital logic circuits.
Still furthermore, the accuracy of ADCs using capacitor arrays depends upon the matching of the capacitance ratios among the capacitors within the array. It is fundamental that the value of a capacitor is proportional to its cross-sectional area. For ADCs, therefore, increased control of the area of the integrated circuit capacitors will directly improve the accuracy of the ADC. The above-referenced copending applications, incorporated herein by this reference, provide high specific capacitance capacitors where the cross-sectional area is defined by the size of a contact via etched through a multilevel dielectric layer, due to the thickness of the multilevel dielectric, for example 1000 nm. While these capacitors can be formed quite accurately, the size of contact vias through multilevel dielectric can vary in the manufacturing process.
It is therefore an object of this invention to provide a capacitor which has a high specific capacitance which has a size which can be more accurately controlled in the fabrication process.
It is another object of this invention to provide a method of forming such a capacitor.
It is another object of this invention to provide such a method which requires relatively low temperature processing.
It is another object of this invention to provide such a method requiring only a single level of polysilicon to form the capacitor.
It is another object of this invention to provide such a capacitor having a low voltage coefficient of capacitance.
It is another object of this invention to provide such a capacitor which may be fabricated at a late stage in the manufacturing process, so that the fabrication steps of the integrated circuit prior to the formation of the capacitor may be standardized with the fabrication steps for integrated circuits not including such capacitors.
It is a further object of this invention to provide such a capacitor which may be fabricated with relatively simple contact etch processing.
Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following description, in conjunction with the drawings.